1. Field of the Invention
The present invention relates to a semiconductor device formed by a semiconductor thin film, and a method of fabricating such a semiconductor device.
2. Background Art
A polysilicon thin-film transistor (hereinafter referred to as TFT) is employed as a load element in a low-power SRAM. The TFT must take a small area and have a large current capacity to form an SRAM having an improved ability and a high degree of integration. The conventional gate all around TFT with a gate electrode wound around a channel polysilicon film has current capacity twice that of a single-gate TFT having the same area.
FIGS. 49 to 51 show a conventional polysilicon thin film transistor. FIG. 49 is a perspective view of the thin-film transistor, FIG. 50 is a sectional view taken on line A-A' in FIG. 49, and FIG. 51 is a sectional view taken on line B-B' in FIG. 49.
Shown in FIGS. 49 to 51 are a silicon substrate 1, a silicon dioxide film 2 formed on a surface of the silicon substrate 1, a channel polysilicon film 6 serving as the channel of a thin-film transistor, a silicon dioxide film 7 formed over the surface of the polysilicon film 6 and the surface of the silicon dioxide film 2, and a gate polysilicon film 8 serving as the gate of the thin-film transistor. The silicon dioxide film 7 between the channel polysilicon film 6 and the gate polysilicon film 8 serves as the gate oxide film of the thin-film transistor.
In this thin-film transistor, the gate 8 consists of a bottom branch gate 8a formed on a surface of an insulating film, and a branch gate 8b branching from the bottom branch gate 8a, extending over the bottom branch gate 8a and having through holes extending therebetween.
The channel 6 is formed so as to branch from one side of the branch gates 8a and 8b, i.e., from one side of the through hole of the gate 8, and pass the through hole of the gate 8.
A gate oxide film 7 is formed between the channel 6, and the branch gates 8a and 8b.
A source/drain region, not shown, is connected to the channel 6 on the sides of the branch gates 8a and 8b, i.e., on the opposite sides of the through hole of the gate 8.
FIGS. 52 to 56 are views for explaining a method of fabricating the foregoing conventional semiconductor device. The conventional semiconductor device fabricating method will be described with reference to FIGS. 52 to 56.
Referring to FIG. 52, a silicon dioxide film 2 of a predetermined thicknesses formed on a silicon substrate 1 by, for example, a thermal oxidation process. A silicon nitride film 3 of a predetermined thickness is deposited by, for example, a reduced pressure CVD process. Then, the silicon nitride film is patterned in a strip of a width corresponding to that of the channel of a desired 5 transistor.
Referring to FIG. 53, polysilicon is deposited over the surface of the workpiece to form a channel silicon film 6. Polysilicon not containing any impurity is deposited in a polysilicon film of a predetermined thickness, and the polysilicon film is patterned by a photolithographic etching process to form the channel silicon film 6 of a desired pattern.
Then, as shown in FIG. 54, the silicon nitride film 3 is removed entirely by, for example, immersing the workpiece in a hot phosphoric acid solution of 150.degree. C. Consequently, an opening is formed in the channel silicon film 6.
Referring to FIG. 55, a gate silicon dioxide film 7 of a predetermined thickness, i.e., a gate insulating film, is deposited over the entire surface of the workpiece so as to cover a first silicon dioxide film 1 and the channel silicon film 6 entirely.
Referring to FIG. 56, a gate polysilicon film 8 doped with phosphorus (i.e. doped polysilicon film) is deposited in a predetermined thickness over the entire surface of the workpiece by a reduced pressure CVD process. The opening formed in the channel silicon film 6 is filled up with the second polysilicon film 8 because the film deposited by the reduced pressure CVD process has an excellent coverage.
Referring to FIGS. 49 to 51, the gate polysilicon film 8 is patterned by a photolithographic etching process in a desired pattern to form a gate electrode.
Then, source/drain implantation is carried out for end portions of the channel silicon film 6 by using the gate electrode 8 superposed on the channel silicon film 6 as a mask. An interlayer insulating film is formed, and wiring lines, such as aluminum lines, are formed so as to extend from the source/drain region to complete a 10 desired transistor, although not shown.
The foregoing gate all around TFT,having the gate electrode wound around the channel polysilicon film has a current capacity twice that of a single-gate TFT taking the same area. If the degree of integration of a low power SRAM increases, a TFT having a smaller area and a greater current capacity is required. However, the conventional TFT is unable to comply satisfactorily with such a request.